Systems, methods and apparatus for local programming of quantum processor elements

ABSTRACT

Systems, methods and apparatus for a scalable quantum processor architecture. A quantum processor is locally programmable by providing a memory register with a signal embodying device control parameter(s), converting the signal to an analog signal; and administering the analog signal to one or more programmable devices.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/950,276, filed Dec. 4, 2007, which claims benefit under 35 U.S.C.119(e) to U.S. provisional patent application Ser. No. 60/868,654, filedDec. 5, 2006, each of which are incorporated herein by reference intheir entirety.

BACKGROUND

1. Field

The present systems, methods and apparatus relate to scalable quantumcomputing and the local programming of quantum processor elements.

2. Description of the Related Art

A Turing machine is a theoretical computing system, described in 1936 byAlan Turing. A Turing machine that can efficiently simulate any otherTuring machine is called a Universal Turing Machine (UTM). TheChurch-Turing thesis states that any practical computing model haseither the equivalent or a subset of the capabilities of a UTM.

A quantum computer is any physical system that harnesses one or morequantum effects to perform a computation. A quantum computer that canefficiently simulate any other quantum computer is called a UniversalQuantum Computer (UQC).

In 1981 Richard P. Feynman proposed that quantum computers could be usedto solve certain computational problems more efficiently than a UTM andtherefore invalidate the Church-Turing thesis. See e.g., Feynman R. P.,“Simulating Physics with Computers”, International Journal ofTheoretical Physics, Vol. 21 (1982) pp. 467-488. For example, Feynmannoted that a quantum computer could be used to simulate certain otherquantum systems, allowing exponentially faster calculation of certainproperties of the simulated quantum system than is possible using a UTM.

Approaches to Quantum Computation

There are several general approaches to the design and operation ofquantum computers. One such approach is the “circuit model” of quantumcomputation. In this approach, qubits are acted upon by sequences oflogical gates that are the compiled representation of an algorithm.Circuit model quantum computers have several serious barriers topractical implementation. In the circuit model, it is required thatqubits remain coherent over time periods much longer than thesingle-gate time. This requirement arises because circuit model quantumcomputers require operations that are collectively called quantum errorcorrection in order to operate. Quantum error correction cannot beperformed without the circuit model quantum computer's qubits beingcapable of maintaining quantum coherence over time periods on the orderof 1,000 times the single-gate time. Much research has been focused ondeveloping qubits with coherence sufficient to form the basicinformation units of circuit model quantum computers. See e.g., Shor, P.W. “Introduction to Quantum Algorithms”, arXiv.org:quant-ph/0005003(2001), pp. 1-27. The art is still hampered by an inability to increasethe coherence of qubits to acceptable levels for designing and operatingpractical circuit model quantum computers.

Another approach to quantum computation comprises using the naturalphysical evolution of a system of coupled quantum systems as acomputational system. This approach does not make critical use ofquantum gates and circuits. Instead, starting from a known initialHamiltonian, it relies upon the guided physical evolution of a system ofcoupled quantum systems wherein the problem to be solved has beenencoded in the terms of the system's Hamiltonian, so that the finalstate of the system of coupled quantum systems contains informationrelating to the answer to the problem to be solved. This approach doesnot require long qubit coherence times. Examples of this type ofapproach include adiabatic quantum computation, cluster-state quantumcomputation, one-way quantum computation, quantum annealing andclassical annealing, and are described, for example, in Farhi, E. etal., “Quantum Adiabatic Evolution Algorithms versus Simulated Annealing”arXiv.org:quant-ph/0201031 (2002), pp 1-16.

Embodiments of Quantum Computers

A quantum computer is any computing device that makes direct use ofquantum mechanical phenomena, such as superposition and entanglement, tosolve computational problems. To date, many different systems have beenproposed and studied as physical realizations of quantum computers.Examples of such systems include the following devices: ion traps,quantum dots, harmonic oscillators, cavity quantum electrodynamicsdevices (QED), photons and nonlinear optical media, heteropolymers,cluster-states, anyons, topological systems, systems based on nuclearmagnetic resonance (NMR), and systems based on spins in semiconductors.For further background on these systems, see Nielsen and Chuang, QuantumComputation and Quantum Information, Cambridge University Press,Cambridge (2000), pp. 277-352; Williams and Clearwater, Explorations inQuantum Computing, Springer-Verlag, New York, Inc. (1998), pp. 241-265;Nielsen, Micheal A., “Cluster-State Quantum Computation”,arXiv.org:quant-ph/0504097 v2 (2005), pp 1-15; and Brennen, Gavin K. etal., “Why should anyone care about computing with anyons?”,arXiv.org:quant-ph/0704.2241 (2007), pp 1-19.

In brief, an example of an ion trap quantum computer is a computerstructure that employs ions that are confined in free space usingelectromagnetic fields. Qubits may be represented by the stableelectronic states of each ion. An example of a quantum dot quantumcomputer is a computer structure that employs electrons that have beenconfined to small regions where their energies can be quantized in sucha way that each dot may be isolated from the other dots. An example of aharmonic oscillator is computer structure that employs a particle in aparabolic potential well. An example of an optical photon quantumcomputer is a computer structure in which qubits are represented byindividual optical photons which may be manipulated usingbeam-splitters, polarization filters, phase shifters, and the like. Anexample of a cavity QED quantum computer is a computer structure thatemploys single atoms within optical cavities where the single atoms arecoupled to a limited number of optical modes. An example of an NMRquantum computer is a computer structure in which qubits are encoded inthe spin states of at least one of the nuclei in the atoms comprising amolecular sample. An example of a heteropolymer quantum computer is acomputer structure that employs a linear array of atoms as memory cells,where the state of the atoms provides the basis for a binary arithmetic.An example of a quantum computer that uses electron spins insemiconductors is the Kane computer, in which donor atoms are embeddedin a crystal lattice of, for example, silicon. An example of atopological quantum computer is a computer structure that employstwo-dimensional “quasiparticles” called anyons whose world lines crossto form braids in a three-dimensional spacetime. These braids may thenbe used as the logic gates that make up the computer structure. Lastly,an example of a cluster-state quantum computer is a computer structurethat employs a plurality of qubits that have been entangled into onequantum state, referred to as a cluster-state. “Cluster-state” generallyrefers to a particular quantum computing method, and those of skill inthe art will appreciate that the present systems, methods and apparatusmay incorporate all forms of quantum computing, including the varioushardware implementations and algorithmic approaches. Those of skill inthe art will also appreciate that the descriptions of variousembodiments of quantum computers provided herein are intended only asexamples of some different physical realizations of quantum computation.The present systems, methods and apparatus are in no way limited by orto these descriptions. Those of skill in the art will also appreciatethat a quantum processor may be embodied in a system other than thosedescribed above.

Qubits

As mentioned previously, qubits can be used as fundamental units ofinformation for a quantum computer. As with bits in UTMs, qubits canrefer to at least two distinct quantities; a qubit can refer to theactual physical device in which information is stored, and it can alsorefer to the unit of information itself, abstracted away from itsphysical device.

Qubits generalize the concept of a classical digital bit. A classicalinformation storage device can encode two discrete states, typicallylabeled “0” and “1”. Physically these two discrete states arerepresented by two different and distinguishable physical states of theclassical information storage device, such as direction or magnitude ofmagnetic field, current, or voltage, where the quantity encoding the bitstate behaves according to the laws of classical physics. A qubit alsocontains two discrete physical states, which can also be labeled “0” and“1”. Physically these two discrete states are represented by twodifferent and distinguishable physical states of the quantum informationstorage device, such as direction or magnitude of magnetic field,current, or voltage, where the quantity encoding the bit state behavesaccording to the laws of quantum physics. If the physical quantity thatstores these states behaves quantum mechanically, the device canadditionally be placed in a superposition of 0 and 1. That is, the qubitcan exist in both a “0” and “1” state at the same time, and so canperform a computation on both states simultaneously. In general, Nqubits can be in a superposition of 2^(N) states. Quantum algorithmsmake use of the superposition property to speed up some computations.

In standard notation, the basis states of a qubit are referred to as the|0

and |1

states. During quantum computation, the state of a qubit, in general, isa superposition of basis states so that the qubit has a nonzeroprobability of occupying the |0

basis state and a simultaneous nonzero probability of occupying the |1

basis state. Mathematically, a superposition of basis states means thatthe overall state of the qubit, which is denoted |Ψ

, has the form |Ψ

=a|0

+b|1

, where a and b are coefficients corresponding to the probabilities |a|²and |b|², respectively. The coefficients a and b each have real andimaginary components, which allows the phase of the qubit to becharacterized. The quantum nature of a qubit is largely derived from itsability to exist in a coherent superposition of basis states and for thestate of the qubit to have a phase. A qubit will retain this ability toexist as a coherent superposition of basis states when the qubit issufficiently isolated from sources of decoherence.

To complete a computation using a qubit, the state of the qubit ismeasured (i.e., read out). Typically, when a measurement of the qubit isperformed, the quantum nature of the qubit is temporarily lost and thesuperposition of basis states collapses to either the |0

basis state or the |1

basis state and thus regaining its similarity to a conventional bit. Theactual state of the qubit after it has collapsed depends on theprobabilities |a|² and |b|² immediately prior to the readout operation.

Superconducting Qubits

One hardware approach to quantum computation uses integrated circuitsformed of superconducting materials, such as aluminum or niobium. Thetechnologies and processes involved in designing and fabricatingsuperconducting integrated circuits are similar to those used forconventional integrated circuits.

Superconducting qubits are a type of superconducting device that can beincluded in a superconducting integrated circuit. Superconducting qubitscan be separated into several categories depending on the physicalproperty used to encode information. For example, they may be separatedinto charge, flux and phase devices, as discussed in, for exampleMakhlin et al., 2001, Reviews of Modern Physics 73, pp. 357-400. Chargedevices store and manipulate information in the charge states of thedevice, where elementary charges consist of pairs of electrons calledCooper pairs. A Cooper pair has a charge of 2e and consists of twoelectrons bound together by, for example, a phonon interaction. Seee.g., Nielsen and Chuang, Quantum Computation and Quantum Information,Cambridge University Press, Cambridge (2000), pp. 343-345. Flux devicesstore information in a variable related to the magnetic flux throughsome part of the device. Phase devices store information in a variablerelated to the difference in superconducting phase between two regionsof the phase device. Recently, hybrid devices using two or more ofcharge, flux and phase degrees of freedom have been developed. See e.g.,U.S. Pat. No. 6,838,694 and US Patent Application No. 2005-0082519.

Examples of flux qubits that may be used include rf-SQUIDs, whichinclude a superconducting loop interrupted by one Josephson junction, ora compound junction (where a single Josephson junction is replaced bytwo parallel Josephson junctions), or persistent current qubits, whichinclude a superconducting loop interrupted by three Josephson junctions,and the like. See e.g., Mooij et al., 1999, Science 285, 1036; andOrlando et al., 1999, Phys. Rev. B 60, 15398. Other examples ofsuperconducting qubits can be found, for example, in Il'ichev et al.,2003, Phys. Rev. Lett. 91, 097906; Blatter et al., 2001, Phys. Rev. B63, 174511, and Friedman et al., 2000, Nature 406, 43. In addition,hybrid charge-phase qubits may also be used.

The qubits may include a corresponding local bias device. The local biasdevices may include a metal loop in proximity to a superconducting qubitthat provides an external flux bias to the qubit. The local bias devicemay also include a plurality of Josephson junctions. Eachsuperconducting qubit in the quantum processor may have a correspondinglocal bias device or there may be fewer local bias devices than qubits.In some embodiments, charge-based readout and local bias devices may beused. The readout device(s) may include a plurality of dc-SQUIDmagnetometers, each inductively connected to a different qubit within atopology. The readout device may provide a voltage or current. DC-SQUIDmagnetometers typically include a loop of superconducting materialinterrupted by at least one Josephson junction.

Superconducting Quantum Processor

A computer processor may take the form of an analog processor, forinstance a quantum processor such as a superconducting quantumprocessor. A superconducting quantum processor may include a number ofqubits and associated local bias devices, for instance two or moresuperconducting qubits. Further detail and embodiments of exemplarysuperconducting quantum processors that may be used in conjunction withthe present systems, methods, and apparatus are described in US PatentPublication No. 2006-0225165; U.S. Provisional Patent Application Ser.No. 60/872,414, filed Jan. 12, 2007, entitled “System, Devices andMethods for Interconnected Processor Topology”; U.S. Provisional PatentApplication Ser. No. 60/956,104, filed Aug. 16, 2007, entitled “Systems,Devices, And Methods For Interconnected Processor Topology”; and U.S.Provisional Patent Application Ser. No. 60/986,554, filed Nov. 8, 2007and entitled “Systems, Devices and Methods for Analog Processing.”

A superconducting quantum processor may include a number of couplingdevices operable to selectively couple respective pairs of qubits.Examples of superconducting coupling devices include rf-SQUIDs anddc-SQUIDs, which couple qubits together by flux. SQUIDs include asuperconducting loop interrupted by one Josephson junction (an rf-SQUID)or two Josephson junctions (a dc-SQUID). The coupling devices may becapable of both ferromagnetic and anti-ferromagnetic coupling, dependingon how the coupling device is being utilized within the interconnectedtopology. In the case of flux coupling, ferromagnetic coupling impliesthat parallel fluxes are energetically favorable and anti-ferromagneticcoupling implies that anti-parallel fluxes are energetically favorable.Alternatively, charge-based coupling devices may also be used. Othercoupling devices can be found, for example, in U.S. Patent PublicationNumber 2006-0147154 and U.S. Provisional Patent Application Ser. No.60/886,253 filed Jan. 23, 2007 and entitled “Systems, Devices, andMethods for Controllably Coupling Qubits”. Respective coupling strengthsof the coupling devices may be tuned between zero and a maximum value,for example, to provide ferromagnetic or anti-ferromagnetic couplingbetween qubits.

Regardless of the specific hardware being implemented, managing a singlequbit may require control over a number of parameters. Conventionally,this requirement has necessitated outside communication (that is,communication from outside of the quantum processor architecture) witheach individual qubit. However, the overall processing power of thequantum computer increases with the number of qubits in the system.Therefore, high capacity quantum computers that exceed the abilities ofconventional supercomputers must manage a large number of qubits andthus the conventional approach of employing outside control overmultiple parameters on each individual qubit requires a complicatedsystem for programming qubit parameters.

Thus, the scalability of quantum processors is limited by the complexityof the qubit parameter control system and there remains a need in theart for a scalable qubit parameter control system.

BRIEF SUMMARY

At least one embodiment may be summarized as a quantum processorincluding a plurality of programmable devices, wherein each programmabledevice is connected to at least one communication conduit; and a memoryadministration system, wherein the memory administration system islinked to at least one programmable device via at least one of thecommunication conduits.

At least one embodiment may be summarized as a method of programming aquantum processor comprising at least one programmable device, themethod including locally programming at least one information storagedevice with a data signal embodying at least one programmable devicecontrol parameter; converting the data signal to an analog signal; andadministering the analog signal to the programmable device.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

In the drawings, identical reference numbers identify similar elementsor acts. The sizes and relative positions of elements in the drawingsare not necessarily drawn to scale. For example, the shapes of variouselements and angles are not drawn to scale, and some of these elementsare arbitrarily enlarged and positioned to improve drawing legibility.Further, the particular shapes of the elements as drawn, are notintended to convey any information regarding the actual shape of theparticular elements, and have been solely selected for ease ofrecognition in the drawings.

FIG. 1A is a schematic diagram of one embodiment of the localprogramming of quantum processor elements according to the presentsystems, methods and apparatus.

FIG. 1B is a schematic diagram of another embodiment of the localprogramming of quantum processor elements.

FIGS. 2A and 2B are flow diagrams of embodiments of methods forrespectively programming and reading quantum processor elements.

FIG. 3 is a schematic diagram of an embodiment of local programming of aquantum processor through a demultiplexer circuit.

DETAILED DESCRIPTION

In the following description, some specific details are included toprovide a thorough understanding of various disclosed embodiments. Oneskilled in the relevant art, however, will recognize that embodimentsmay be practiced without one or more of these specific details, or withother methods, components, materials, etc. In other instances,well-known structures associated with quantum processors, such asquantum devices, coupling devices and control systems, includingmicroprocessors and drive circuitry, have not been shown or described indetail to avoid unnecessarily obscuring descriptions of the embodimentsof the present systems, methods and apparatus. Throughout thisspecification, the words “element” and “elements” are used to encompass,but are not limited to, all such structures, systems and devicesassociated with quantum processors, as well as their relatedprogrammable parameters.

Unless the context requires otherwise, throughout the specification andclaims which follow, the word “comprise” and variations thereof, suchas, “comprises” and “comprising” are to be construed in an open,inclusive sense, that is, as “including, but not limited to.”

Reference throughout this specification to “one embodiment,” “anembodiment” or “another embodiment” means that a particular referentfeature, structure or characteristic described in connection with theembodiment is included in at least one embodiment. Thus, the appearancesof the phrases “in one embodiment,” “in an embodiment” or “anotherembodiment” in various places throughout this specification are notnecessarily all referring to the same embodiment. Furthermore, theparticular features, structures or characteristics may be combined inany suitable manner in one or more embodiments.

It should be noted that, as used in this specification and the appendedclaims, the singular forms “a,” “an” and “the” include plural referentsunless the content clearly dictates otherwise. Thus, for example,reference to “a quantum processor” includes a single quantum processoror two or more quantum processors. It should also be noted that the term“or” is generally employed in its sense including “and/or” unless thecontent clearly dictates otherwise.

Furthermore, it should be noted that while a portion of thisspecification and the appended claims describes the application of thisdisclosure in a quantum processor comprising superconducting fluxqubits, those of skill in the art will appreciate that the methodsdescribed herein may easily be adapted to apply to other forms ofquantum processors.

The headings provided herein are for convenience only and do notinterpret the scope or meaning of the embodiments.

In accordance with the present systems, methods and apparatus, ascalable technique for quantum computing involving local programming ofquantum processor elements is described. Throughout this specificationand the appended claims, the term “quantum processor” is used todescribe a system that comprises at least two qubits and at least onedevice, such as a qubit coupler, for communicating information betweenat least two qubits. Some embodiments of a quantum processor may includetens, hundreds, thousands, or even millions of qubits and qubitcouplers. In some embodiments, the components of a quantum processor maybe entirely contained within a single structure, such as asuperconducting quantum processor chip. In other embodiments, thecomponents of a quantum processor may be distributed over a plurality ofstructures with a means for communicating information therebetween.

FIG. 1A shows an exemplary quantum processor 100 which includes memoryadministration system 101 and three programmable devices 121, 122, 123.Throughout this specification and the appended claims, the terms“programmable device” and “programmable devices” are used to describeany of a variety of components in a quantum processor for whichprogramming is desired. Examples of programmable devices include qubits,qubit couplers, specific components of qubits and qubit couplers, andthe like. For example, a superconducting flux qubit may include twocomponents: a closed superconducting current path and a compoundJosephson junction, and separate data signals may be programmed intoboth of these components individually.

Those of skill in the art will appreciate that quantum processor 100 maybe scaled to include any number of devices by simply scaling the devicesshown in FIG. 1A accordingly. Furthermore, although FIG. 1A showsquantum processor 100 as one physical structure, the components ofquantum processor 100 may be divided into a plurality of separatephysical units that are communicably connected by a system ofcommunication conduits. For example, quantum processor 100 may include aplurality of distinct processor chips, or a multi-chip module, whereinspatially separated components may be communicably connected by a systemof communication conduits. Reference throughout this specification andthe appended claims to a “communication conduit” or a plurality of“communication conduits” encompasses all means of signal transfer,including but not limited to electrical wires, conductive traces,magnetic (inductive) coupling, capacitive coupling, fiber-optics, andthe like.

In FIG. 1A, memory administration system 101 comprises a string ofmemory registers 111, 112, 113 which are used to administer signalsrepresentative of data, such as N-bit digital signals, to eachprogrammable device 121-123 in quantum processor 100. Those of skill inthe art will appreciate that the terms “administer”, “administering”,“administration” and the like are used herein to encompass, but are notlimited to, all manner of generating, managing, storing, operating uponand transferring the data signals. The N-bit signals may be programmedto represent various parameters that influence the behavior ofprogrammable devices 121-123. For illustration, 8-bit signals andserially connected 8-bit memory registers 111-113 are shown in FIG. 1A,but those of skill in the art will appreciate that signals of any bitlength or resolution may be employed and that memory registers 111-113may be connected in another manner or may not be connected at all, i.e.,they may be connected in parallel, in an X-Y addressable array, througha demultiplexer circuit, in a network including at least one packetrouter, or they may each be independently controlled and each have theirown individual communication lines A, B, C, D.

As shown in FIG. 1A, the data signals administered by memory registers111-113 are digital signals, however those of skill in the art willappreciate that data signals of other forms may be employed. Beforebeing applied to programmable devices 121-123, the digital signals maybe converted into analog signals by digital-to-analog converters (DACs)131, 132, 133. Each respective DAC 131-133 may receive the digital bitsof an N-bit signal and use this N-bit digital signal to produce at leastone analog signal which may then be administered to at least one ofprogrammable devices 121-123. In some embodiments, such as that shown inFIG. 1A, this administration is accomplished via intermediate couplingdevices 141, 142, 143. The intermediate coupling devices 141-143 mayeach be connected to a coupler activation line and beactivated/deactivated by the coupler activation line. In someembodiments, intermediate coupling devices 141-143 may be connected inseries to a single coupler activation line as illustrated in FIG. 1A.Thus, in such embodiments, a signal is only administered or applied froma DAC 131-133 to a programmable device 121-123 when a correspondingintermediate coupling device 141-143 is activated by the coupleractivation line. For example, a signal may be administered from DAC 131to programmable device 121 when intermediate coupling device 141 isactivated by the coupler activation line. In some embodiments, a coupleractivation line may be analog variable such that intermediate couplingdevices 141-143 may provide controllable levels of partial couplingbetween DACs 131-133 and programmable devices 121-123. In someembodiments, a coupler activation line may only be ON/OFF controllable,such that intermediate coupling devices 141-143 may provide onlycontrollable ON/OFF coupling between DACs 131-133 and programmabledevices 121-123. Other embodiments of the present systems, methods andapparatus may omit the intermediate coupling devices 141-143 and insteadsignals may be coupled directly from DACs 131-133 to programmabledevices 121-123.

By employing the present systems, methods and apparatus, at least aportion of the control communication may be contained within quantumprocessor 100 while external input includes the programming of the N-bitsignals via communication lines A-D, and, in some embodiments, thecontrol of intermediate coupling devices 141-143 via at least onecoupler activation line. As such, the number of communication linesrequired to connect quantum processor 100 to an external system isgreatly reduced and becomes essentially independent of the number ofprogrammable devices in quantum processor 100.

One skilled in the art will recognize that a DAC may be applied toconvert digital signals to analog, analog signals to digital, or toperform both operations simultaneously or interchangeably, depending onthe signal direction. As such, the system described in FIG. 1A may alsobe operated in reverse, whereby signals from programmable devices121-123 are coupled to DACs 131-133 via intermediate coupling devices141-143. The signals may then be converted into digital representationswhich may be administered or applied to memory registers 111-113 andtransmitted to an external reading system.

The present systems, methods and apparatus are not linked to aparticular type of quantum processor and its associated programmabledevices. Rather, the present systems, methods and apparatus may beapplied to any form of quantum processor. In some embodiments, quantumprocessor 100 may be a superconducting quantum processor comprising aplurality of superconducting flux qubits coupled by a plurality ofprogrammable qubit couplers, such as those described in US PatentPublication Nos. 2006-0225165 and 2006-0147154, and in Harris, R. etal., “Sign and Magnitude Tunable Coupler for Superconducting FluxQubits”, arXiv.org:cond-mat/0608253 (2006), pp 1-5. Since such qubitsand their associated couplers are designed to manage flux signals, theN-bit signals from memory registers 111-113 may be administered in theform of discrete magnetic flux quanta. Memory registers 111-113 may thentake the form of superconducting shift registers, such as single fluxquantum (SFQ) shift registers or the flux-based superconducting shiftregisters described in U.S. Provisional Patent Application Ser. No.60/913,980, filed Apr. 25, 2007, and entitled “Adiabatic SuperconductingQubit Logic Devices And Methods.” In some embodiments, thesuperconducting shift registers may be serially linked as illustrated inFIG. 1A, or they may be connected in parallel, or they may be connectedin an X-Y addressable array, or they may be connected to a routingsystem. The N-bit signal loaded into each register may be representeddigitally by discrete magnetic flux quanta within the superconductingshift registers. Each of the superconducting shift registers 111-113 maybe inductively or galvanically coupled to a respective superconductingDAC 131-133, where the digital magnetic flux quanta may be used toproduce at least one analog supercurrent. Thus, in some embodiments amemory register, such as memory register 111 and a DAC, such as DAC 131,may be realized within the same physical structure. Examples ofsuperconducting DACs are described in U.S. Provisional PatentApplication Ser. No. 60/917,884, filed May 14, 2007, entitled “ScalableSuperconducting Flux Digital-To-Analog Conversion Using ASuperconducting Inductor Ladder Circuit”; U.S. Provisional PatentApplication Ser. No. 60/917,891, filed May 14, 2007, entitled “Systems,Methods, And Apparatus For A Scalable Superconducting FluxDigital-To-Analog Converter”; and U.S. Provisional Patent ApplicationSer. No. 60/975,487, filed Sep. 26, 2007, and entitled “Systems, Methodsand Apparatus for a Differential Superconducting Flux Digital-to-AnalogConverter.”

In some embodiments, the at least one analog supercurrent that is outputby a DAC may be inductively coupled to at least one programmable device121-123 via at least one intermediate coupling device 141-143 byactivating the coupler activation line. In other embodiments, the atleast one analog supercurrent may be inductively coupled directly to atleast one of programmable devices 121-123. As previously described, insome embodiments the system may also be operated in reverse to producedigital output from the SFQ shift registers based on analog input fromone or more programmable devices 121-123.

In some embodiments of the present systems, methods and apparatus, aplurality of DACs may be coupled to a single programmable device. FIG.1B is a schematic diagram of such an embodiment for the localprogramming of quantum processor elements. The embodiment illustrated inFIG. 1B is similar to that illustrated in FIG. 1A, except that in FIG.1B two DACs 132 and 133 are coupled to a single programmable device 124,while DACs 132 and 133 are also each coupled to a respective memoryregister 112 and 113. This coupling scheme can provide control over therate at which programmable device 124 is programmed from an initialstate X to a programmed state Y, effectively realizing an arbitrarywaveform generator. In the embodiment shown in FIG. 1A, eachprogrammable device 121-123 is coupled to a single DAC (131-133,respectively) and therefore each programmable device 121-123 isprogrammed at the same time and at the same rate. However, in theembodiment shown in FIG. 1B, programmable device 124 is coupled to twoDACs 132 and 133 and this allows a degree of control over the time andrate at which programmable device 124 is programmed. Those of skill inthe art will appreciate that while only one programmable device 124 isshown as being coupled to two DACs 132 and 133 in FIG. 1B, all or anynumber of the programmable devices in a quantum processor may be coupledto two or any number of DACs.

FIG. 2A is a flow diagram of a method 200 for programming the elementsof a quantum processor (such as, for example, quantum processor 100 ofFIG. 1A) according to an embodiment of the present systems, methods andapparatus. Those of skill in the art will appreciate that while FIG. 2Arefers to all devices in singular form, method 200 may be applied over aplurality of devices. In act 201 of method 200, a binary signal isprogrammed or written to a memory register (such as one or more ofmemory registers 111-113 from FIG. 1A). In act 202, the binary signal isconverted into a analog signal. In act 203, the analog signal isadministered or applied to one or more programmable devices of thequantum processor, such as programmable devices 121-123 from FIG. 1A.Thus, acts 201 through 203 may all be completed within the dimensions ofthe quantum processor, thus reducing the need for communication withexternal programming systems.

FIG. 2B is a flow diagram of a method 250 for reading information fromreadable devices by essentially operating method 200 in reverse. Thoseof skill in the art will appreciate that while FIG. 2B refers to alldevices in singular form, method 250 may be applied over a plurality ofdevices. In act 251, a signal is output by or read from the readabledevice and converted into a digital representation. In act 252, thedigital representation of the signal is output to or read-out by anothersystem. Again, acts 251 to 252 may be completed within the dimensions ofthe quantum processor, thus reducing the need for communication withexternal programming systems.

As previously discussed, a variety of coupling schemes may beimplemented to program data storage devices, such as memory registers111-113. For instance, memory registers 111-113 may be serially coupledto communication lines A-D as illustrated in FIGS. 1A and 1B. In otherembodiments, memory registers 111-113 may be coupled in parallel tosimilar communication lines. In some embodiments of the present systems,methods and apparatus, the data storage devices may be programmedthrough a routing system; an example of such a routing system is ademultiplexer circuit.

FIG. 3 is a schematic diagram of an embodiment of local programming of aquantum processor 300 through a demultiplexer circuit 350. Asillustrated in FIG. 3, quantum processor 300 includes memoryadministration system 301, which is similar to memory administrationsystem 101 from FIG. 1A except that it includes a demultiplexer circuit350 that may be used to rout signals to data storage devices 311-313. Inoperation, demultiplexer 350 may receive a signal through at least oneof communication lines A and B and, through a sequence of internalrouting procedures, direct the signal towards a specific output channel.The specific output channel may correspond to at least one of datastorage devices 311-313. The general operation of a demultiplexer isunderstood in the art; as such, those of skill in the art willappreciate that demultiplexer 350 may include additional signal inputlines. In some embodiments, demultiplexer 350 may include a plurality ofrouting devices arranged in logical rows to form a logical binary tree.Demultiplexer 350 may include additional signal input lines (not shown)such that each logical row of routing devices is controlled by arespective signal input line.

The above description of illustrated embodiments is not intended to beexhaustive or to limit the embodiments to the precise forms disclosed.Although specific embodiments of and examples are described herein forillustrative purposes, various equivalent modifications can be madewithout departing from the spirit and scope of the disclosure, as willbe recognized by those skilled in the relevant art. The teachingsprovided herein of the various embodiments can be applied to otherquantum computing systems, methods and apparatus, not necessarily theexemplary quantum computing systems, methods and apparatus generallydescribed above.

For instance, the foregoing detailed description has set forth variousembodiments of the systems, methods and apparatus via the use of blockdiagrams, schematics, and examples. Insofar as such block diagrams,schematics, and examples contain one or more functions and/oroperations, it will be understood by those skilled in the art that eachfunction and/or operation within such block diagrams, flowcharts, orexamples can be implemented, individually and/or collectively, by a widerange of hardware, software, firmware, or virtually any combinationthereof.

The various embodiments described above can be combined to providefurther embodiments.

All of the U.S. patents, U.S. patent application publications, U.S.patent applications, foreign patents, foreign patent applications andnon-patent publications referred to in this specification including, butnot limited to: U.S. Pat. No. 6,838,694; US Patent Publication No.2005-0082519; US Patent Publication No. 2006-0225165; U.S. ProvisionalPatent Application Ser. No. 60/872,414, filed Jan. 12, 2007, entitled“System, Devices and Methods for Interconnected Processor Topology”;U.S. Provisional Patent Application Ser. No. 60/956,104, filed Aug. 16,2007, entitled “Systems, Devices, And Methods For InterconnectedProcessor Topology”; U.S. Provisional Patent Application Ser. No.60/986,554, filed Nov. 8, 2007, entitled “Systems, Devices and Methodsfor Analog Processing”; US Patent Publication No. 2006-0225165; USPatent Publication No. 2006-0147154; U.S. Provisional Patent ApplicationSer. No. 60/913,980, filed Apr. 25, 2007, and entitled “AdiabaticSuperconducting Qubit Logic Devices And Methods”; U.S. ProvisionalPatent Application Ser. No. 60/917,884, filed May 14, 2007, entitled“Scalable Superconducting Flux Digital-To-Analog Conversion Using ASuperconducting Inductor Ladder Circuit”; U.S. Provisional PatentApplication Ser. No. 60/917,891, filed May 14, 2007, entitled “Systems,Methods, And Apparatus For A Scalable Superconducting FluxDigital-To-Analog Converter”; and U.S. Provisional Patent ApplicationSer. No. 60/975,487, filed Sep. 26, 2007, entitled “Systems, Methods andApparatus for a Differential Superconducting Flux Digital-to-AnalogConverter” are incorporated herein by reference, in their entirety andfor all purposes. Aspects of the embodiments can be modified, ifnecessary, to employ systems, circuits and concepts of the variouspatents, applications and publications to provide yet furtherembodiments.

These and other changes can be made to the embodiments in light of theabove-detailed description. In general, in the following claims, theterms used should not be construed to limit the invention to thespecific embodiments disclosed in the specification and the claims, butshould be construed to include all possible embodiments along with thefull scope of equivalents to which such claims are entitled.Accordingly, the scope of the invention shall only be construed anddefined by the scope of the appended claims.

1. A quantum computing system comprising: an external programmingsystem; a quantum processor; and a number of communication linesproviding communication between the external programming system and thequantum processor, wherein the quantum processor further comprises: anumber of programmable devices; and a memory administration systemincluding a plurality of communication conduits, wherein the memoryadministration system provides communication between the communicationlines and at least some of the communication conduits to administer datasignals from the external programming system to the programmabledevices, and wherein the number of programmable devices is greater thanthe number of communication lines.
 2. The quantum computing system ofclaim 1 wherein the quantum processor includes at least one programmabledevice that is formed of a material that is superconducting below acritical temperature.
 3. The quantum computing system of claim 1 whereinat least one of the communication conduits of the memory administrationsystem is formed of a material that is superconducting below a criticaltemperature.
 4. The quantum computing system of claim 1 wherein thequantum processor includes at least one programmable device that isselected from the group consisting of: a closed superconducting currentpath, a compound Josephson junction, a superconducting flux qubit, asuperconducting charge qubit, a superconducting phase qubit, asuperconducting hybrid qubit, a qubit coupler, a superconducting qubitcoupler, a quantum dot, a trapped ion, a trapped neutral atom, animpurity, a nuclear spin qubit, an electronic spin qubit, and a photonicqubit.
 5. The quantum computing system of claim 1 wherein the memoryadministration system includes at least one digital-to-analog converter(DAC).
 6. The quantum computing system of claim 5 wherein the DACincludes a superconducting DAC, and wherein digital signals arerepresented by discrete magnetic flux quanta.
 7. The quantum computingsystem of claim 1 wherein the memory administration system includes anX-Y addressable array.
 8. The quantum computing system of claim 1wherein the memory administration system includes a demultiplexercircuit.
 9. A method of programming a quantum processor, wherein thequantum processor includes a number of programmable devices and a memoryadministration system, the method comprising: defining a plurality ofprogrammable parameters corresponding to the number of programmabledevices by an external programming system; transmitting a plurality ofsignals embodying the plurality of programmable parameters from theexternal programming system to the memory administration system via anumber of communication lines that is less than the number ofprogrammable devices; and administering the plurality of signalsembodying the plurality of programmable parameters to the number ofprogrammable devices by the memory administration system.
 10. The methodof claim 9 wherein the memory administration system includes at leastone digital-to-analog converter (DAC) and the plurality of signalsembodying the plurality of programmable parameters are digital signals,and further comprising: converting the plurality of signals embodyingthe plurality of programmable parameters from digital signals to analogsignals by the at least one DAC before administering the plurality ofsignals embodying the plurality of programmable parameters to the numberof programmable devices.
 11. The method of claim 9 wherein administeringthe plurality of signals embodying the plurality of programmableparameters to the number of programmable devices by the memoryadministration system includes routing the plurality of signalsembodying the plurality of programmable parameters to the number ofprogrammable devices via an X-Y addressable array.
 12. The method ofclaim 9 wherein administering the plurality of signals embodying theplurality of programmable parameters to the number of programmabledevices by the memory administration system includes routing theplurality of signals embodying the plurality of programmable parametersto the number of programmable devices via a demultiplexer circuit.